1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device having an ECC (Error Checking and Correction) function.
2. Description of the Background Art
An information processing system employs various types of memory devices for storing information. One of such memory devices is a semiconductor memory device, which is made of a semiconductor such as silicon.
FIG. 11 illustrates the structure of a memory cell array of a general semiconductor memory device. As shown in FIG. 11, the memory cell array of such a semiconductor memory device generally includes a plurality of memory cells MC which are arranged in a matrix of rows and columns. Word lines WL1 to WLn are provided in correspondence to respective rows of the memory cell array. Memory cells MC of one row are connected to each of the word lines WL1 to WLn. Bit lines (or bit line pairs) CL1 to CLm are provided in correspondence to respective columns of the memory cell array. Memory cells MC of one column are arranged on each of the bit lines (or bit line pairs) CL1 to CLm.
In selection of a 1-bit memory cell MC, one word line WLi (i=1 to n) and one bit line (or bit line pair) CLj (j=1 to m) are selected. A memory cell MC which is arranged in correspondence to the intersection of the selected word line WLi and the selected bit line (or bit line pair) CLj is selected, and data can be written in or read from the selected memory cell MC.
The structures of memory cells are varied with the types of semiconductor memory devices. The semiconductor devices include a random access memory (RAM) which can write and read information in a random sequence, a nonvolatile semiconductor memory device which can store information in a nonvolatile manner, and the like. An example of the nonvolatile semiconductor memory device is a mask ROM (read only memory) for storing fixed data.
FIGS. 12A and 12B illustrate the structure of a memory cell which is employed for a mask ROM. Referring to FIG. 12A, the memory cell comprises a MOS (insulated gate) transistor having a gate which is connected to a word line WL, a drain which is connected to a bit line CL and a source which is connected to the ground potential.
Referring to FIG. 12B, the memory cell includes impurity regions 502 and 504 which are formed on a surface of a semiconductor substrate 500 and a control gate 508 which is formed oh a channel region 506 between the impurity regions 502 and 504 with a gate insulating film 509 underlaid. The control gate 508 is connected to the word line WL and the impurity region 502 provides a drain (or source) region which is connected to the bit line CL, and the impurity region 504 provides a source (or drain) region which is connected to the ground potential. In general, the impurity regions 502 and 504 are formed of N-type regions of high impurity concentration, and the semiconductor substrate 500 is prepared from a P-type semiconductor substrate.
In order to adjust the threshold voltage of the memory cell transistor, ions are implanted into the channel region 506. The threshold voltage of this memory cell transistor is shifted by such ion implantation into the channel region 506.
As shown in FIG. 13, a memory cell transistor has a depletion type threshold voltage (curve 516 in FIG. 13) or an enhancement type threshold voltage (curve 517 in FIG. 13) by ion implantation into the channel region 506. FIG. 13 illustrates the relation between the gate voltage of the memory cell transistor and a drain current flowing through this transistor. The axis of ordinates indicates the drain current Ids, and the axis of abscissas indicates the gate voltage Vgs.
The direction in which the threshold voltage of the memory cell transistor by ion implantation is shifted is determined by the species of implanted ions. FIG. 13 shows threshold voltages of a depletion type memory cell transistor and an enhancement type memory cell transistor as Vth2 and Vth1 respectively. In the depletion type memory cell transistor, the drain current Ids flows when its gate voltage Vgs exceeds the threshold voltage Vth2. In the enhancement type memory cell transistor, on the other hand, the drain current Ids flows when its gate voltage Vgs exceeds the threshold voltage Vth1.
It is assumed that a memory cell transistor having the depletion type threshold voltage stores a logic "1" data, while a memory cell transistor having the enhancement type threshold voltage stores a logic "0" data.
In the depletion type memory cell transistor corresponding to a state storing information "1", an inversion layer is formed in the channel region 506 to flow the drain current Ids even if the potential at the control gate 508 (word line WL) is 0 V. In the enhancement type memory cell transistor corresponding to a state storing information "0", no drain current Ids flows when a voltage of 0 V is applied to the control gate 508 (word line WL). The information is read according to presence/absence of the drain current Ids on the bit line CL in selection of the word line WL.
As an alternative to the aforementioned setting of the threshold voltage by ion implantation, information may be written in the mask ROM according to presence/absence of contact between the source of the memory cell transistor and the bit line or between the drain and the ground potential.
In a general semiconductor memory device, the rate of occurrence of defective bits is increased following increase in storage capacity. In order to repair such defective bits, a redundant row and/or a redundant column is so provided as to replace the defective bits by the redundant row or column, thereby repairing the defective bits in a redundancy structure. When the storage capacity is further increased, however, the number of the defective bits may be so increased that all the defective bits may not be repaired by such a redundancy structure. Therefore, the semiconductor memory device is provided with an ECC function for checking errors in stored information and correcting as-checked errors.
FIG. 14 schematically illustrates the overall structure of a general mask ROM which is provided with an ECC function. Referring to FIG. 14, the mask ROM includes a memory cell array 600 of the aforementioned memory cells which are arranged in a matrix of rows and columns. This memory cell array 600 includes an information bit region 602 for storing information bits and an error checking bit region 604 storing error checking bits for checking errors of the information bits.
The mask ROM further includes an X decoder 606 which decodes row address signal bits RA0 to RAn for selecting a corresponding row (word line) of the memory cell array 600, a Y decoder 608 which receives column address signal bits CA0 to CAm for generating signals for selecting corresponding columns (bit lines) of the memory cell array 600, a Y gate circuit 610 for connecting selected columns of the memory cell array 600 to internal data lines (not shown) in response to outputs from the Y decoder 608, and a sense amplifier circuit 612 for detecting and amplifying information on the columns selected by the Y gate circuit 610.
In general, a word is formed by a plurality of bits, and the Y decoder 608 generates signals for simultaneously selecting a plurality of columns of the memory cell array 600. Thus, a prescribed number of information bits are read from the information bit region 602, while an error checking bit associated with the information bits is read from the region 604. If a word line corresponds to a word, the Y decoder 608 may be omitted.
The mask ROM further includes an ECC circuit 614 for checking errors with respect to the data (the information bits and the error checking bit) detected and amplified by the sense amplifier circuit 612 and correcting as-checked errors, and an output buffer 616 for outputting correct information bits received from the ECC circuit 614 to the exterior. Referring to FIG. 14, information bits D0 to Dp are shown to be outputted in parallel to form a word of (p+1) bits, for example.
The ECC circuit 614 checks and corrects an error in the information bits on the basis of the information bits and the error checking bit received from the sense amplifier circuit 612, and transmits the corrected information bits to the output buffer 616. The error checking bit may be formed by a linear code employing a parity bit. In such a linear code, an error checking bit is generated from the information bits in accordance with a parity check equation. Such a linear code includes a well-known Hamming code, which can correct a single error. A general ECC circuit which is employed in a semiconductor memory device is provided with a one bit error checking and correcting function, or a two bit error checking and one bit error correcting function. In order to check and correct errors, a syndrome is generally generated from as-read information bits and error checking bit.
The mask ROM further includes a control circuit 618 which receives control signals (chip enable and output enable signals) /CE and /OE for controlling activation timings of the sense amplifier circuit 612 and the output buffer 616. In this mask ROM, the X decoder 606 and the Y decoder 608 statically operate to decode the supplied address signal bits RA0 to RAn and CA0 to CAm respectively. The control circuit 618 activates the sense amplifier circuit 612 in response to the chip enable signal /CE, and activates the output buffer 618 in response to the output enable signal /OE.
When the storage capacity of such a mask ROM is increased, NAND type memory cells are generally used, in order to improve integration and density of the memory cell array.
FIG. 15 illustrates configurations of NAND type memory cells. Referring to FIG. 15, a prescribed number of bits of memory cells AMC1 to AMCn are connected in series between a bit line BL2 and a source line SL, while a prescribed number of memory cells BMC1 to BMCn are connected in series between a bit line BL1 and the source line SL. The source line SL is connected to the ground potential GND. The bit lines BL1 and BL2 are connected to the Y gate circuit 610 shown in FIG. 14, while only one of the bit lines BL1 and BL2 is connected to the sense amplifier circuit 612 through the Y gate circuit 610. In the structure shown in FIG. 15, further, only one of the memory cell units may be connected to the source line SL depending on whether the selected bit line BL is denoted by an even or odd number, to form a current path between the selected bit line BL and the source line SL.
FIGS. 16A and 16B illustrate a plane arrangement and a sectional structure of a memory cell unit, i.e., a set of NAND-connected memory cells. Referring to FIG. 16A, an impurity diffusion region 300 is provided, and interconnection layers 1-1 to 1-n forming control gates of memory cell transistors, i.e., word lines, are arranged at prescribed intervals in a direction perpendicular to the impurity diffusion layer 300. Channel regions are formed in intersections between the diffusion layer 300 and respective ones of the interconnection layers 1-1 to 1-n. The diffusion layer 300 is formed zigzag, and an end (source region 2) is connected to an interconnection layer 5 forming a source line through a source contact 20 and another end (drain region 3) is connected to an interconnection layer 4 forming a bit line through a drain contact 30. The interconnection layers 5 and 4 forming the source and bit line are arranged in parallel to each other.
In the arrangement shown in FIG. 16A, two memory cell units (NAND-connected memory cells) are connected to one bit line 4. In this case, a selection transistor may be arranged between the bit line 4 and the source line 5 for forming a current path, in order to select one of the memory cell units. Similarly, two memory cell units are connected to one source line interconnection layer 5.
As shown in FIG. 16B, the drain region 3 is connected to the bit line interconnection layer 4 through the contact 30, and impurity layers 25-1 to 25-n are arranged between the drain region 3 and the source region 2 at prescribed intervals. Respective intervals between the drain region 3 and the impurity regions 25-1 to 25-n and the source region 2 are determined by the interconnection layers 1-1 to 1-n which are formed thereon. As clearly understood from FIG. 16B showing a section taken along the line A--A in FIG. 16A, a plurality of memory cells are connected to the interconnection layer 4 forming a bit line through one contact 30. The number of the bit line contact per memory cell is reduced and no grounding wire may be provided for each memory cell, whereby the area of the memory cell array can be reduced. The operation of the memory cells shown in FIGS. 15, 16A and 16B is now described.
In order to select a memory cell AMCj (j=1 to n) in FIG. 15, a word line wlj is set at a low potential level and remaining word lines wl1 to wl(j -1) and wl(j+1) to wln are set at high potential levels. A memory cell storing information "1" has a depletion type threshold voltage Vth of not more than 0 V, while that storing information "0" has an enhancement type threshold voltage Vth exceeding 0 V and being not more than the high potential level. When the selected memory cell AMCj stores information "1", this memory cell is such a depletion type transistor that a drain current Ids flows even if the potential at its control gate is at a low level. When the selected memory cell AMCj stores information "0", on the other hand, this memory cell is in an OFF state since the potential of its control gate is at a low level (0 V), with no flowing of the drain current Ids.
The potentials of the nonselected word lines are at high levels, whereby the nonselected memory cells are in ON states to feed drain currents Ids regardless of information stored therein since the control gates thereof are at high potential levels. Thus, a current or no current flows on the bit line BL2 in response to the information stored in the selected memory cell AMCj. The sense amplifier circuit 612 detects flow/non-flow of the current on the bit line BL2 to determine whether the read information is "1" or "0", thereby generating corresponding data.
In order to select a memory cell BMCj, the bit line BL1 is similarly selected by the Y gate circuit 610 to be connected to the sense amplifier circuit 612. Read data is generated in response to flow/non-flow of a current on the bit line BL1 at this time.
When a word is formed by a plurality of bits, i.e., when a plurality of information bits are simultaneously read, the memory cell array 600 is divided into blocks in correspondence to respective bits. As shown in FIG. 17, the information bit storage region 602 and the error checking bit storage region 604 of the memory cell array 600 are divided into blocks B#0 to B#M and P#0 to P#N respectively in correspondence to respective bits.
The word lines are arranged in common to respective blocks. In reading, one word line WL is so selected that data bits Q0 to QM and P0 to PN are read from respective blocks B#0 to B#M and P#0 to P#N. The as-read data bits Q0 to QM and P0 to PN are supplied to the ECC circuit through the sense amplifier circuit 612, to be subjected to error checking and correction.
In general, an ECC circuit which is provided in a semiconductor memory device has a one bit error checking and correcting function. Namely, such an ECC circuit generates a syndrome from the received data Q0 to QM and P0 to PN, to check and correct an error in accordance with this syndrome.
When data of a 1-bit memory cell (denoted by symbol X in FIG. 18A) is erroneous among memory cells connected to one word line WL as shown in FIG. 18A, it is possible to correct the error.
When a plurality of data bits are erroneous among data of the memory cells which are connected to one word line WL as shown in FIG. 18B, however, it is impossible to check and correct the errors by the ECC circuit.
When a word line is made defective by particles or the like, there is a high probability that data read from memory cells which are connected to this word line are erroneous, since such defects localize if the particles are large-sized. When a defective word line is selected, there is a high probability that a plurality of errors are caused in the data Q0 to QM and P0 to PN which are simultaneously selected and read out, leading to incapability of error checking and correction. Thus, defective word lines can be repaired only in a low rate, and the yield of such semiconductor memory devices is deteriorated.